According to Moore’s Law, the transistors in SOCs double about every two years through shrinking CMOS processes. This shrink drives junction depth and smaller Gate Oxide Thicknesses which results in higher sensitivity to ESD events. Some devices can only support ESD...
New Levels of Power Density Silicon MOSFETs has used extensively in most power application since 35 years ago that displaced the bipolar transistor. In these 10 years, Gallium Nitride (GaN) is already an established semiconductor material, employed extensively in LED...
As a result of Ultra_Low Rss(on) demand for recent Quick-Charge application to reduce severe thermal-effect, CSP (Chip Scale Package) type MOSFET will be the ONLY solution against traditional wire-bonding packages. SakuraFET™, designed by JPD Labo. In Takasaki, Japan,...
From audio to video, from normal speed data rate to high speed date rate, I/O ports are everywhere to connect devices for personal computing. Not only provide robustness for ESD strikes, but also provide Low Clamping and Low Capacitance to protect system chips, UBIQ...
Along with technology innovation , the transmission rate for massive data between devices rapidly increases. High speed interfaces with data rates in Gbit/ sec range ONLY allow minimum additional capacitance on the line. Due to miniaturization, the smaller the size,...
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