Applications Diagram

Smart Power Stage Module for High Power Density and Efficiency.
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SMART POWER STAGE

HPC Solutions

High Performance Computing

DC/DC Power Conversion for Graphics, Motherboard, Notebook, Server, Datacenter, AI Telecom Applications

Power Density Aggressively Growing

ASIC CPU GPU power density aggressively growing

  • DPWM Controller development for higher phase counts operation need.
  • Higher Power Density Power Stage development MCM / Monolithic.

Smart Power Stages

Integration of industry’s best in class technology MOSFETs with intelligent gate drivers through Infineon’s superior packaging technologies results in a rich, high quality power stage portfolio that can be used in Servers, Storage, Datacom, Telecom and Consumer applications to power CPU GPU SoC ASIC Memory rails.

uPI’s power stage portfolio ranges to 120 A peak current and are available in multiple packages These power stages offer excellent power conversion efficiency and thermal performance that result in best power density combined with fast protection features to enable reliable and robust operation over lifetime of the end system.

Accurate output current and temperature telemetry also helps improve system intelligence and processor performance significantly.

Driving Density and Power Requirements

Exponential Growth in Processing Power

What makes a Smart Power Stage?

Power Stage Focus

High Efficiency within TDC and heavy load.

High Accurate System Reporting.

Current┃Temperature

Smart Protection Features and Communication

OCP┃OTP┃UVLO┃HMSP┃Pre-OVP

Fault Repotting

Thermal Dissipation

Robust Design

Minimize BOM and Space

Smart Power Stage Classification

Power Stage Trends MCM and Monolithic

Typical VR Solution for VCORE solution

PWM : Input signal that drives the power MOSFETs in a half bridge configuration.

IOUT : Output signal communicates the load seen by the VR

TOUT : Output Signal communicates the highest temperature in a multiphase configuration and Report to VR when fault happen in SPS

Smart Power Stage – Classification

Power Density Aggressively Growing

Client Computing

High Performance Computing

Enterprise Server

Monolithic Type will be the<br /> majority applied in Client.

Monolithic Type will be the majority applied in Client.

  • Lower TDC , but higher Peak Current for CPU transient performance.
  • IMON Accuracy (+/ 3%)
  • Smaller Package for cost optimization ( BOM & Space)
  • Majority in Monolithic Package : 3×4 / 3×5 / 4×5 / 4×6 / 5×6
MCM will be the majority applied in HPS / AI / Server

MCM will be the majority applied in HPS / AI / Server

  • High Power Density (High TDC and Peak Current)
  • High IMON Accuracy (+/ 2%)
  • High Reliability
  • TLVR Support paring with Inductors
  • Majority in MCM Package 3×4 / 4×6 / 5×6

VR Design Considerations

Limitation in Conventional VR

Future in TLVR

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Eff & Transient

  • Transient performance is primarily determined by Lc.
  • TL primary side self inductance can be relatively large to maintain high efficiency.
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Cost

  • No need to add excessive output capacitors to balance between efficiency and transient.
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Benefits

  • The TLVR improves transient & efficiency performance, while cut the capacitor cost by 70%.